NXP

S32V234
Demoboard SBC-S32V234

i.MX 8 – Arm® Cortex®-A53

Topology: Other

Original publication on 2019-03-06, revision 3

Description

ARM® Cortex®-A53, 64-bit CPU– Up to 1000 MHz Quad ARM Cortex-A53– 32 KB/32 KB I-/D- L1 Cache– NEON MPE co-processor– Dual precision FPU– 2 clusters with 2 CPUs and 256 KB L2 cache each– Memory Management Unit– GIC Interrupt Controller– ECC/parity error support for its memories– Generic timers– Fault encapsulation by hardware for redundantexecuted application software on multiple corecluster• ARM Cortex-M4, 32-bit CPU– Up to 133 MHz– 16 KB/16 KB I-/D- L1 Cache– 32+32 KB tightly coupled memory (TCM)– ECC/parity support for its memories• Clocks– Phase Locked Loops (PLLs)– 1 external crystal oscillator (FXOSC)– 1 FIRC oscillator• System protection and power management features– Flexible run modes to consume low power based onapplication needs– Peripheral clock enable register can disable clocks tounused modules, thereby reducing currents– Power gating of unused A53 cores and GPU– Low and high voltage warning and detect– Hardware CRC module to support fast cyclicredundancy checks (CRC)– 120-bit unique chip identifier– Hardware watchdog– eDMA controller with 32 channels (withDMAMUX)– Extended Resource Domain Controller Memory interfaces– 32-bit DRAM Controller with support for LPDDR2/DDR3/DDR3L - Data rate of up to 1066 MT/s at 533 MHz clockfrequency with ECC (SEC-DED-TED) triple error detection support for subregion– QuadSPI supporting Execute-In-Place (XIP)– Boot flash fault detection and correction using two-dimensional parity.– Triple fault detection and single fault correction scheme for external DDR-RAM including address/page fault detection.• Video input interfaces, Image processing, graphics processing, display– Display Control Unit (2D-ACE) with 24-bit RGB, GPU frame buffer decoding– GPU GC3000 with frame buffer compression– 2x VIU (Video interface unit) for camera input– 2x MIPICSI2 with four lanes for camera input (support 1080 pixel @ 30 fps)– Image signal processor (ISP), supporting 2x1 or 1x2 megapixel @ 30 fps and 4x2 megapixel for subset of functions(exposure control, gamma correction)– 2x APEX2-CL Image cognition processor. APEX-642CL comprises two Array Processing Unit (APU) coresconfigurable as single SIMD engine with 64 16-bit Computational Units (CU), or configurable as two core MIMDengines with 32 16-bit CUs each.– CUs are comprised of four Functional Units: 16-bit Multiplier, Load Store Unit, ALU, and Shifter– JPEG video decoder (8/12-bit)– H.264 video decoder (8/10/12-bit), High-intra and constrained baseline formats– H.264 video encode (8/10/12-bit), High-intra only– Fast DMA for data transfers between DRAM and System RAM with CRC• Human-Machine Interface (HMI)– GPIO pins with interrupt support, DMA request capability, digital glitch filter– Configurable slew rate and drive strength on all output pins• System RAM– 4 MB On-Chip System RAM with ECC

Characteristics

  • ARM® Cortex®-A53, 64-bit CPU– Up to 1000 MHz Quad ARM Cortex-A53– 32 KB/32 KB I-/D- L1 Cache– NEON MPE co-processor– Dual precision FPU– 2 clusters with 2 CPUs and 256 KB L2 cache each– Memory Management Unit– GIC Interrupt Controller– ECC/parity error support for its memories– Generic timers– Fault encapsulation by hardware for redundantexecuted application software on multiple corecluster• ARM Cortex-M4, 32-bit CPU– Up to 133 MHz– 16 KB/16 KB I-/D- L1 Cache– 32+32 KB tightly coupled memory (TCM)– ECC/parity support for its memories• Clocks– Phase Locked Loops (PLLs)– 1 external crystal oscillator (FXOSC)– 1 FIRC oscillator• System protection and power management features– Flexible run modes to consume low power based onapplication needs– Peripheral clock enable register can disable clocks tounused modules, thereby reducing currents– Power gating of unused A53 cores and GPU– Low and high voltage warning and detect– Hardware CRC module to support fast cyclicredundancy checks (CRC)– 120-bit unique chip identifier– Hardware watchdog– eDMA controller with 32 channels (withDMAMUX)– Extended Resource Domain Controller Memory interfaces– 32-bit DRAM Controller with support for LPDDR2/DDR3/DDR3L
  • Data rate of up to 1066 MT/s at 533 MHz clockfrequency with ECC (SEC-DED-TED) triple error detection support for subregion– QuadSPI supporting Execute-In-Place (XIP)– Boot flash fault detection and correction using two-dimensional parity.– Triple fault detection and single fault correction scheme for external DDR-RAM including address/page fault detection.• Video input interfaces, Image processing, graphics processing, display– Display Control Unit (2D-ACE) with 24-bit RGB, GPU frame buffer decoding– GPU GC3000 with frame buffer compression– 2x VIU (Video interface unit) for camera input– 2x MIPICSI2 with four lanes for camera input (support 1080 pixel @ 30 fps)– Image signal processor (ISP), supporting 2x1 or 1x2 megapixel @ 30 fps and 4x2 megapixel for subset of functions(exposure control, gamma correction)– 2x APEX2-CL Image cognition processor. APEX-642CL comprises two Array Processing Unit (APU) coresconfigurable as single SIMD engine with 64 16-bit Computational Units (CU), or configurable as two core MIMDengines with 32 16-bit CUs each.– CUs are comprised of four Functional Units: 16-bit Multiplier, Load Store Unit, ALU, and Shifter– JPEG video decoder (8/12-bit)– H.264 video decoder (8/10/12-bit), High-intra and constrained baseline formats– H.264 video encode (8/10/12-bit), High-intra only– Fast DMA for data transfers between DRAM and System RAM with CRC• Human-Machine Interface (HMI)– GPIO pins with interrupt support, DMA request capability, digital glitch filter– Configurable slew rate and drive strength on all output pins• System RAM– 4 MB On-Chip System RAM with ECC

Products

  Order Code SPEC Product series L
(µH)
IR
(A)
ISAT
(A)
RDC typ.
(mΩ)
RDC max.
(mΩ)
fres
(MHz)
Bauform Version Montageart Typ IR 1
(A)
Arbeitsspannung
(V (AC))
Verpackung Z @ 100 MHz
(Ω)
Zmax
(Ω)
TC Zmax IR 2
(mA)
Anwendung PCB/Kabel/Panel Modularity Pins Wire Section Interface typ Gender Pins Poles VPE H
(mm)
Betätigungskraft
(g)
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