Cyclone V Device

Topologie: Boost
Schaltfrequenz (max.): 800.00 kHz

Erstveröffentlichung am 30.09.2011, Version 2012.12.28


The Cyclone® V devices are designed to simultaneously accommodate the shrinking power consumption, cost, and time-to-market requirements; and the increasing bandwidth requirements for high-volume and cost-sensitive applications. Enhanced with integrated transceivers and hard memory controllers, the Cyclone V devices are suitable for applications in the industrial, wireless and wireline, military, and automotive markets.


  • TSMC's 28-nm low-power (28LP) process technology• 1.1 V core voltage• Wirebond low-halogen packages• Multiple device densities with compatible package footprints for seamless migrationbetween different device densities• RoHS-compliant optionsEnhanced 8-input ALM with four registers• M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)• Memory logic array block (MLAB)—640-bit distributed LUTRAM where you canuse up to 25% of the ALMs as MLAB memory• Native support for up to three signal processing precision levels(three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the samevariable-precision DSP block• 64-bit accumulator and cascade• Embedded internal coefficient memory• Preadder/subtractor for improved efficiencyDDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC supportPCI Express® (PCIe®) Gen2 and Gen1 (x1, x2, or x4) hard IP withmultifunction support, endpoint, and root port• Up to 550 MHz global clock network• Global, quadrant, and peripheral clock networks• Clock networks that are not used can be powered down to reduce dynamic power• Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)• Integer mode and fractional mode• 875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter• 400 MHz/800 Mbps external memory interface• On-chip termination (OCT)• 3.3 V support with up to 16 mA drive strength• 614 Mbps to 5.0 Gbps integrated transceiver speed• Transmit pre-emphasis and receiver equalization• Dynamic partial reconfiguration of individual channels• Single or dual-core ARM Cortex-A9 MPCore processor-up to 800 MHz maximumfrequency with support for symmetric and asymmetric multiprocessing• Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller,NANDflash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART,controller area network (CAN), serial peripheral interface (SPI), I2C interface, andup to 85 HPS GPIO interfaces• System peripherals—general-purpose timers, watchdog timers, direct memory access(DMA) controller, FPGA configuration manager, and clock and reset managers• On-chip RAM and boot ROM• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweightHPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves inthe HPS, and vice versa• FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface tothe multiport front end (MPFE) of the HPS SDRAM controller• ARM CoreSight™ JTAG debug access port, trace port, and on-chip trace storage• Tamper protection—comprehensive design protection to protect your valuable IPinvestments• Enhanced advanced encryption standard (AES) design security features• CvP• Partial and dynamic reconfiguration of the FPGA• Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP)x8 and x16 configuration options


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Material Version RDC typ.
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Typ Pins
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